Capacitors are widely used in integrated circuits. One of the most commonly used capacitors is the metal-oxide-metal (MOM) capacitor. FIG. 1 illustrates a typical MOM capacitor, which includes a bottom plate 2, a top plate 6, and an insulation layer 4 therebetween. The bottom plate 2 and top plate 6 are formed of conductive materials.
As is known in the art, the capacitance of a MOM capacitor is proportional to its area and the dielectric constant (k) of the insulation layer, and is inversely proportional to the thickness of the insulation layer. Therefore, to increase the capacitance, it is preferable to increase the area and k value and to reduce the thickness of the insulation layer. However, the thickness and k value are often limited by the technology used for forming the capacitor. For example, the thickness cannot be less than what the existing technology allows. On the other hand, since the MOM capacitors are often formed in low-k dielectric layers, the ability to increase the k value is also limited.
Methods for increasing the area of the capacitor have also been explored. A problem associated with increased area is that greater chip area is required. This dilemma is solved by the introduction of vertical (multi-layer) capacitors. A typical vertical MOM capacitor 10 is shown in FIGS. 2, 3 and 4. FIG. 2 illustrates a perspective view of a capacitor 10, which includes two metal electrodes 12 and 14 separated by dielectric materials. Each of the metal electrodes 12 and 14 form a three-dimensional structure. For clarity, metal electrode 12 is shown as unpatterned, and metal electrode 14 is patterned with dots.
Each of the metal electrodes 12 and 14 include more than one layer connected by vias, and each layer is formed in a metallization layer commonly used for the formation of interconnect structures. FIG. 3 illustrates a top view of a first metal layer (please refer to the middle layer in FIG. 2). Metal electrode 12 includes fingers 122 and a bus 121 that connects all the fingers 122. Metal electrode 14 includes fingers 142 and a bus 141 that connects all the fingers 142. Fingers 122 and 142 are placed in an alternating pattern with a very small space between the neighboring fingers. Therefore, each finger 122/142 forms a sub capacitor(s) with its neighboring fingers 142/122 or a bus 141/121. The total capacitance is equivalent to the sum of the sub capacitors.
FIG. 4 illustrates a top view of the capacitor 10 in a second metallization layer (refer to the top or the bottom layer in FIG. 2), which overlies or underlies the first metallization layer. Typically, the direction of the fingers in the second metallization layer is orthogonal to the direction of fingers in the first metallization layer. Similarly, electrodes 12 and 14 in the second metallization layer include buses 121 and 141 and a plurality of fingers 122 and 142, respectively. Typically, buses 121 in all the layers have similar shapes and sizes and are overlapped vertically. Buses 141 in all the layers also have similar shapes and sizes and are overlapped vertically. Vias 16 connect buses 121 in the first and the second metallization layers, thereby forming an integral electrode 12. Similarly, vias 18 connect buses 141 in neighboring layers, thereby forming an integral electrode 14.
In addition to the capacitance in each of the metallization layers, the capacitance of capacitor 10 also includes portions created by the overlap between the different layers. FIG. 5 illustrates electrode 12 in the first metallization layer and electrode 14 in the second metallization layer. Note that overlapped portions 19 contribute to the total capacitance of capacitor 10.
In the conventional capacitor shown in FIGS. 2 through 5, fingers 122 are orthogonal to the connecting bus 121, and fingers 142 are orthogonal to the connecting bus 141. The capacitors having such a structure thus require rectangular-shaped chip areas. If an irregular chip area is available, only a sub area having a rectangular shape can be used to form a capacitor. The chip area usage is thus low. Therefore, a more flexible capacitor design is needed.